System and method for removing oxide from a sensor clip assembly

ABSTRACT

According to embodiments of the present disclosure, a method for removing oxide includes placing a sensor chip assembly having an oxide layer formed on a portion thereof within an enclosed and controlled environment. The portion of the sensor chip assembly is exposed to a reactive gas and a UV light to result in a substantial removal of the oxide layer formed on the portion of the sensor chip assembly.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.13/107,195, filed May 13, 2011, the disclosure of which is incorporatedby reference herein in its entirety.

TECHNICAL FIELD

This invention relates generally to a system and method for removingoxide, and more particularly, to a system and method for removing nativeoxide in the preparation of interconnects for used in sensor chipassemblies.

BACKGROUND OF THE INVENTION

Focal Planes (FPA) consist of a compound semiconductor sensing element(i.e., detector) and a silicon readout array (i.e., CMOS read-OutIntegrated Circuit (ROIC)) joined on a pixel by pixel level. In infraredsensing systems that utilize flip chip assemblies of FPAs, indium bumptechnology is used to bond the detector array to the ROIC. Specifically,each of the detector array and the ROIC include indium bumps formed onthe surface thereof. The indium bumps on the opposing surfaces of eachdevice may be mated and joined together in a process calledhybridization.

Although indium has proved to be a good material for these applications,layers of native oxide may be formed on the indium bumps during thefabrication of the FPA. The native oxide may prevent properinterconnection between the detector array and ROIC. As the number ofpixels increases and the sizes of the pixels decreases, the formation ofnative oxide on indium bumps may pose significant challenges. As such,the native oxide must be removed prior to the hybridization process.

Known techniques for removing the native oxide include a mechanicalscrubbing process that includes rubbing the mated indium bumps againsteach other until the oxide layer breaks. This process may impose harmfulmechanical stress on chip contacts and have a negative impact on yield.For example, as the surface area of the detector array increases, theforce that is required to break through the oxide increasesexponentially and may exceed the limits that may be withstood bycommercially available devices. As a result, mechanical scrubbing mayinduce crystal damage and have detrimental effects on deviceperformance. Other known techniques include the use of cleaning agentsor acid etches that may also cause corrosion and/or degradation of theindium. Accordingly, known techniques for chemically or mechanicallyremoving the native oxide layers may result in damage to FPA componentsand the fabrication of defective circuits.

SUMMARY OF THE INVENTION

According to embodiments of the present disclosure, a method forremoving oxide includes placing a sensor chip assembly having an oxidelayer formed on a portion thereof within an enclosed and controlledenvironment. The portion of the sensor chip assembly is exposed to areactive gas and a UV light to result in a substantial removal of theoxide layer formed on the portion of the sensor chip assembly.

Embodiments of the disclosure may provide numerous technical advantages.For example and according to one embodiment, the native oxide layersformed on the indium bumps of a focal plane array may be removed priorto the hybridization process. In particular, the indium bumps that areused to form the interconnects may be simultaneously exposed to acombination of UV light and a reactive gas. This combination of UV lightand the reactive gas may result in the substantial removal of the nativeoxide from the indium bumps. However, because the components of thefocal plane array are not subject to mechanical forces during theremoval of the native oxide, damage resulting from mechanical stress isprevented. A further technical advantage may be that the combination ofUV light and the reactive gas results in removal of the native oxidelayers at temperatures that are below the melting temperature of indium.Accordingly, the native oxide may be removed from a focal plane arraywithout having a negative impact on yield or negatively effecting deviceperformance.

Certain embodiments of the present disclosure may include some, all, ornone of the above advantages. One or more other technical advantages maybe readily apparent to those skilled in the art from the figures,descriptions, and claims included herein.

BRIEF DESCRIPTION OF THE DRAWINGS

To provide a more complete understanding of the present invention andthe features and advantages thereof, reference is made to the followingdescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1A illustrates an example Focal Plane Array (FPA), according tocertain embodiments of the present disclosure;

FIG. 1B illustrates example indium bump interconnections in the exampleFPA of FIG. 1A, according to certain embodiments of the presentdisclosure;

FIG. 2 illustrates an example system for removing native oxide fromcomponents of the FPA, according to certain embodiments of the presentdisclosure; and

FIG. 3 illustrates an example method for removing native oxide fromcomponents of the FPA, according to certain embodiments of the presentdisclosure.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a schematic of an example sensor chip assembly 100,according to certain embodiments of the present disclosure. In aparticular embodiment, sensor chip assembly 100 includes a conventionalhybrid Focal Plane Array infrared detector assembly (FPA) utilizing flipchip technology. Accordingly, as depicted, sensor chip assembly 100includes a compound semiconductor sensing element that may include anintrinsic or extrinsic detector array 102 that is generally aligned withan integrated circuit 104. In particular embodiments, where sensor chipassembly 100 comprises a FPA, integrated circuit 104 may include a CMOSread-out integrated circuit (ROIC). As will be described in more detailbelow, indium bump or other interconnect technology may be used to joindetector array 102 and integrated circuit 104 on a pixel by pixel level.

As depicted, sensor chip assembly 100 includes a compound semiconductordetector array having a plurality of sensors 108 arranged in a squarearray. Similarly, integrated circuit 104 may also include a siliconsubstrate 110 having a number of contact pads 112 that generallycorresponds with the number of sensors 108. Contact pads 112 may includeone or more layers of various contact metals and may, in someembodiments, include a layer of gold plating. In one particularembodiment, contact pads 112 may have a surface area of approximately 10microns×10 microns. For example, in one particular embodiment, each ofdetector array 102 and integrated circuit 104 may include a 4K×4K arrayof a total of 16 million individual sensors 108 and contact pads 112,respectively. However, it is generally recognized that the describedembodiment is just one example of a FPA. Sensor chip assembly 100 mayinclude any number of sensors 108 and contact pads 112 as is required bypixel size and capacitance requirements.

Interconnects 114 are formed between each sensor 108 and a correspondingone of contact pads 112. As can be seen from FIG. 1B, each interconnect114 may be comprised of two indium bumps 116 a and 116 b. Specifically,a first indium bump 116 a may be formed on a surface of a sensor 108 ofdetector array 102, and a second indium bump 116 b may be formed on asurface of contact pad 112 of integrated circuit 104. Detector array 102and integrated circuit 104 may then be brought together in a controlledenvironment for hybridization. Specifically, first and second indiumbumps 116 a and 116 b may be mated and joined by soldering orcold-welding, in certain embodiments.

Because of its cryogenic stability, thermal and electrical conductivity,self-adhesive nature, and relative ease of application, indium hasproved to be a good material for forming interconnects 114. However, itis generally recognized that, in ambient conditions, native oxide mayform quickly on indium bumps 116 a and 116 b prior to the hybridizationof detector array 102 and integrated circuit 104. The formation ofnative oxide is a natural occurrence when sensor chip assembly 100 isexposed to oxygen. For example, a layer of approximately 50 to 100angstroms of indium oxide may form on indium bumps 116 a and 116 b whenintegrated circuit device is exposed to oxygen in the ambient air. Thepresence of the indium oxide on the opposing surfaces of indium bumps116 a and 116 b, however, prevents proper interconnection between thedetector array 102 and readout array 104. Accordingly, it may benecessary to remove or substantially remove the indium oxide layer fromindium bumps 116 a, 116 b just prior to hybridization.

Prior techniques for removing the native oxide negatively affect theyield of units produced since components of the sensor chip assembly 100may be damaged during the oxide removal process. For example, one suchtechnique includes a mechanical scrubbing process in which the matedindium bumps 116 a and 116 b are rubbed against each other until thenative oxide layer breaks. However, the forces required to result in thebreaking up of the native oxide layer may impose harmful mechanicalstress on indium bumps 116 a and 116 b. Damage to bumps 116 a and 116 bmay prevent proper electrical connection and have detrimental effects ondevice performance. As further examples, an acid etch or clean-up agentmay be used to result in the chemical removal of the native oxide.However, the acid etch may also etch the material of indium bumps 116 aand 116 b and other surfaces around the indium bumps and result in thefabrication of defective devices Likewise, the use of a cleaning agent(such as flux) may require the application of a solvent to removecontaminants from the soldered connection. The solvents and fluxes mustbe nonconductive and noncorrosive and used in a manner that keeps thedissolved flux residue from contact surfaces. Any flux remaining in thejoin corrodes the connection and creates a defective device. As afurther problem, environmental laws and agreements may eventuallyprohibit the use of these solvents.

FIG. 2 illustrates an example system 200 for removing native oxide fromcomponents of a sensor chip assembly 202, such as a FPA, according tocertain embodiments of the present disclosure. In contrast to thetechniques formerly used for the removal of native oxide, system 200provides a controlled environment 204 in which at least one controller206 operates to simultaneously expose sensor chip assembly 202 to areactive gas 208 and UV light 210. Controller 206 may include anyhardware or software necessary for controlling the components of system200. In certain embodiments, controller 206 may include a processor orother computing device.

System 200 includes a reactive chamber 212 that is configured to receiveat least a portion of sensor chip assembly 202 prior to hybridization.As depicted, sensor chip assembly 202 includes first component 214 andsecond component 216. First component 214 may include a compoundsemiconductor detector array such as detector array 106 that isdescribed above with respect to FIG. 1. Likewise, second component 216may include an integrated circuit such as integrated circuit 104. Inparticular embodiments, second component 216 may include a CMOS ROIC.However, while both the first component 214 and the second component 216are depicted as being contained within reactive chamber 212, it isgenerally recognized that either or both of first and second components214 and 216 may be placed within reactive chamber 212 at any one time.As describe below, where both components are simultaneously received inreactive chamber 212, the oxide layers formed on either or both ofcomponents 214 and 216 may be removed and components 214 and 216 maythen be joined during the hybridization process while the components arecontained in reactive chamber 212.

Within reactive chamber 212, sensor chip assembly 202 may be exposed toa combination of reactive gas 208 and UV light 210 to result in thesubstantial removal of a native oxide layer from the interconnectcomponents. The removal of the native oxide layer may be performed priorto the hybridization of the sensor chip assembly 202. Since thecombination of reactive gas 208 and UV light 210 do not cause electricalor chemical damage to components, system 200 provides for thesubstantial removal of native oxide without having a detrimental effecton interconnect components or device performance. Additionally, thecombination allows for the oxide layer to be removed at temperaturesthat are less than the melting temperature of the interconnectcomponents.

In particular embodiments, system 200 may include a modified UV Ashersuch as those that are commonly found in clean rooms. Such devices maybe conventionally used to burn carbon off of the surfaces of carboncomponents of an integrated circuit device. Thus, system includes a UVlight source 217 for generating UV light 210. Additionally, system 200is modified to include a reactive gas supply 218 that operates as asource of reactive gas 208. For example, in one example embodiment, aSAMCO UV/Ozone Asher may be modified to include reactive gas supply 218.In certain embodiments, reactive gas 208 may include a formic acid vaporor methanoic acid. For example, in particular embodiments, reactive gas208 may be selected from the group consisting of Aminic Acid, Formylicacid, Hydrogen carboxylic acid, Hydroxymethanone, Hydroxy(oxo)methane,Metacarbonic acid, Oxocarbinic acid, and Oxomethanol.

As described above, reactive chamber 212 is configured to receive sensorchip assembly 202. While sensor chip assembly 202 may be substantiallysimilar to sensor chip assembly 100, sensor chip assembly 202 isdepicted to include FPA components prior to hybridization. Additionally,both of first component 214 and second component 216 are depicted ashaving native oxide layers formed on at least a portion thereof.Specifically, first component 214 has a first interconnect 220 on whichan oxide layer 222 is formed. Similarly, second component 216 has asecond interconnect 224 on which an oxide layer 226 is formed. Nativeoxide layers 222 and 226 may be naturally formed under ambientconditions when first and second components 214 and 216 are exposed tooxygen. In particular embodiments, native oxide layers 222 and 226 maybe approximately 50 to 100 Angstroms thick.

System 200 maintains the temperature within the enclosed and controlledenvironment 204 at a temperature that is below the melting temperatureof the interconnect components. For example, in a particular embodiment,the temperature of the controlled environment 204 may be maintainedbelow a temperature of 156 degrees Celsius. System 200 may thensimultaneously expose first and second components 214 and 216 to UVlight 210 and reactive gas 208 for a predefined period of time that issufficient to result in the substantial removal of native oxide layers222 and 226 formed on interconnect components 220 and 224, respectively.

As depicted, system 200 may also include a nitrogen supply 230configured to provide nitrogen 232 to reactive chamber 212. Inparticular embodiments, nitrogen 232 may be pumped into reactive chamber212 to substantially purge reactive chamber 212 of oxygen 234 Oxygen 234may be removed from reactive chamber 212 via a vent 236. The substantialremoval of oxygen 234 may create an inert environment and prevent thefurther formation of native oxide 222 and/or 226 on interconnectcomponents 220 and 224, respectively. In particular embodiments, theoxygen content within the controlled environment 204 of reactive chamber212 may be monitored and maintained at a level that is less than 60parts per million. In addition to purging system 200 of unwanted oxygen234, nitrogen 232 may also be used to dilute the concentration ofreactive gas 208 and, thus, maintain the concentration of reactive gas208 at desired levels.

The operation of system 200 may be best understood in conjunction withFIG. 3, which illustrates an example method for removing native oxidefrom components of a FPA, according to certain embodiments of thepresent disclosure. The method begins at step 300 with the placing ofsensor chip assembly 202 within the enclosed and controlled environment204 prior to hybridization. As depicted, sensor chip assembly 202includes a FPA device such as the one illustrated in FIGS. 1A and 1B.However, as described above with regard to FIG. 2, one or more layers ofnative oxide 222 and 226 are formed on either or both of first component214 and second component 216. For example, native oxide layers 222 and226 may be formed on the surface of interconnect components such asindium bumps. In one example embodiment, native oxide layers 222 and 226may be of a thickness on the order of 50 to 100 Angstroms when formed inambient conditions prior to the hybridization process.

At step 302, oxygen 234 may be substantially purged from the controlledenvironment 204. For example, and as described above, nitrogen 232 fromnitrogen supply 230 may be injected into the controlled environment 204.The inflow of nitrogen 232 may force oxygen 234 to be vented fromreactive chamber 212 through one or more vents 236. In particularembodiments, the oxygen content within reactive chamber 212 may bemonitored and maintained at a level that is less than 60 parts permillion.

At step 304, the layers of native oxide 222 and 226 formed on thesurface of interconnects 220 and 224 may be exposed to reactive gas 208supplied reactive gas supply 218. As describe above, reactive gas 208may include a formic acid vapor and may be selected from the groupconsisting of Aminic Acid, Formylic acid, Hydrogen carboxylic acid,Hydroxymethanone, Hydroxy(oxo)methane, Metacarbonic acid, Oxocarbinicacid, and Oxomethanol, in particular embodiments. In one particularembodiment, the concentration of reactive gas 208 may selected such thatthe controlled environment 204 is made up of approximately 40%-50% ofreactive gas 208 and approximately 50-60% of nitrogen 232. For example,in one particular embodiment, the controlled environment 204 may includeapproximately 42% of reactive gas 208 and 58% of nitrogen 232.

At step 306 and while sensor chip assembly 202 is being exposed toreactive gas 208, sensor chip assembly 202 may be simultaneously exposedto UV light 210. In a particular embodiment, for example, sensor chipassembly 202 may be simultaneously exposed to reactive gas 208 and UVlight 210 for a predetermined amount of time that is at least 5 minutes.Generally, the predetermined amount of time may be more than 5 minutesbut less than 10 minutes. When applied to sensor chip assembly 202 forthe predetermined amount of time, the combination of reactive gas 208and UV light 210 may result in the substantial removal of the oxidelayers 222 and 226 formed on the surfaces of interconnects 220 and 224.Specifically, UV light 210 may operate to disassociate the formic acidvapor to create a plurality of CO and H₂ radicals. The CO and H₂radicals may then operate as reducing agents to remove oxide layers 222and 226 from interconnects 220 and 224. One example chemical reaction(where reactive gas 208 comprises HCOOH) may include:

HCOOH+In₂O₃→In+CO₂+H₂O

Though the above reaction of reactive gas 208 and oxide layers 222 and226, results in the native oxide being removed from interconnects 220and 224, reactive gas 208 does not chemically react with interconnects220 and 224. As such, interconnects 220 and 224 are kept intact.

In addition to assisting in the disassociation of the reactive gas 208,UV light 210 may also enable reactive gas 208 to remove native oxide 222and 226 at lower temperatures. It may be generally recognized thatindium oxide remains solid up to 850 degrees Celsius. Above 850 degreesCelsius, the indium oxide layers 222 and 226 may sublime. Thistemperature is much higher than the melting point of indium, which isapproximately 156 degrees Celsius. However, interconnects 220 and 224may not considerably change shape even if heated above 156 degreesCelsius due to the stiff mechanical properties of the In₂O₃ jacketsurrounding interconnects 220 and 224. Nevertheless, it is desirable toremove native oxide layers 222 and 226 at a temperature that is lowerthan the melting point of the material forming interconnects 220 and224. Thus, in particular embodiments, it is desirable to remove nativeoxide layers 222 and 226 at a temperature that is lower than the meltingpoint of indium. Because the presence of UV light 210 aids in thedisassociation of reactive gas 208 into reducing agent radicals,reactive gas 208 may be used to remove native oxide 222 and 226 at atemperature that is below the melting temperature of Indium or anothermetal forming interconnects 220 and 224. For example, where sensor chipassembly 202 is exposed to both UV light 210 and reactive gas 208 at atemperature of approximately 150 degrees Celsius, the combination mayresult in the substantial removal of native oxide 222 and 226 after anexposure time of approximately 5 minutes. In contrast, where UV light210 is omitted and sensor chip assembly 202 is exposed only to reactivegas 208 at an increased temperature of approximately 160 degreesCelsius, reactive gas 208 alone may not result in the substantialremoval of native oxide 222 and 226 even after an exposure time ofapproximately 5 minutes.

Following the substantial removal of oxide layers 222 and 226, ahybridization process may then be performed at step 308. Thehybridization process results in the joining of interconnects 220 and224. For example, the hybridization process may include cold solderingof interconnects 220 and 224 formed of indium bumps.

Although the present invention has been described with severalembodiments, diverse changes, substitutions, variations, alterations,and modifications may be suggested to one skilled in the art, and it isintended that the invention encompass all such changes, substitutions,variations, alterations, and modifications as fall within the spirit andscope of the appended claims.

1. A system for removing oxide comprising: a reactive chamber configured to provide an enclosed and controlled environment for receiving a sensor chip assembly; a first gas supply coupled to the reactive chamber, the first gas supply maintaining a supply of reactive gas; a UV lamp operable to generate UV light within the reactive chamber, and at least one controller in communication with the first gas supply and the UV light, the at least one controller operable to simultaneously expose the sensor chip assembly to the reactive gas and the UV light to result in the substantial removal of a layer of oxide formed on a portion of the sensor chip assembly.
 2. The system of claim 1, wherein the at least one controller is configured to maintain a temperature of the enclosed and controlled environment below a temperature of approximately 156 degrees Celsius.
 3. The system of claim 1, wherein the sensor chip assembly comprises a Focal Plane Array.
 4. The system of claim 1, wherein: the sensor chip assembly comprises one or more of a detector array and a readout integrated circuit; and the portion on which the oxide layer is formed comprises an interconnect of one or more of the detector array and the readout integrated circuit.
 5. The system of claim 1, wherein the sensor chip assembly comprises: a first component comprising a detector array having a first interconnect component; and a second component comprising a readout integrated circuit having a second interconnect component, and, wherein the portion of the sensor chip assembly on which the oxide layer is formed comprises one or more of the first interconnect component and the second interconnect component.
 6. The system of claim 1, wherein the reactive gas comprises a formic acid selected from the group consisting of methanoic acid, Aminic acid, Formylic acid, Hydrogen carboxylic acid, Hydroxymethanone, Hydroxy(oxo)methane, Metacarbonoic acid, Oxocarbinic acid, and Oxomethanol.
 7. The system of claim 1, wherein the controller is operable to expose the portion of the integrated circuit device to the reactive gas and the UV light for at least 5 minutes. 